|
The heart of the reference design is the Virtex-II Pro device with RocketIO™ Multi-Gigabit Transceivers (MGT), serving as the interface to the full-mesh backplane. The full-mesh card also allows application flexibility by reserving an area of the board for a plug-in "personality module" (PM). You can use the PM to implement any application-specific line card and easily connect to the full-mesh card through the included headers. A picture of the circuit board included in the Design Kit is shown in Figure 1 below while a high-level block diagram of the board architecture is shown in Figure 2.
The kit includes the circuit board, a mesh fabric example design, test and example designs as well as a complete board support package and extensive user guide. Software, card cages, design services and even power supplies are also available from Avnet and third party Design Kit participants.
Figure 1: PICMG ATCA development board
PICMG ATCA Design Kit:
The PICMG ATCA Design Kit accelerates development and deployment of a broad-range of applications. It uses a standard footprint that leverages existing infrastructure while ensuring interoperability through compliance with the PICMG standard. The kit provides a 15 channel, one port full mesh fabric interface, supports port rates up to 3.125 Gbps and includes an area for customers to develop application-specific personality modules.
The kit uses a Virtex-II Pro FPGA based Mesh Fabric Reference Design that includes all PICMG 3.0 defined card and shelf management functionality. The management firmware executes on one of the Virtex-II Pro's PowerPC processors running an embedded Linux operating system.
The Mesh Fabric Reference Design is included with the purchase of the Design Kit and is a great starting point for application development.
Figure 2: PICMG ATCA Block Diagram
Mesh Fabric Reference Design:
The Mesh Fabric Reference Design from Xilinx is a fully functional FPGA design that enables cost-optimized and highly flexible serial mesh backplanes with Mesh Technology on Xilinx Solutions. The example design has been targeted for Virtex-II Pro FPGAs with all the baseline functions required for a mesh backplane fabric interface, including ingress and egress datapath blocks, serial link interface blocks utilizing RocketIO MGTs, and a management interface block for control plane access to internal control and status registers. For ease of connection to other IP, the design utilizes the standard Local Link interface.
PICMG 3.0 specifies card and shelf management functionalities that are also implemented in the reference design. Figure 3 shows a high-level block diagram of the PowerPC based control plane logic developed using Xilinx's Embedded Developer's Kit (EDK).
The Mesh Fabric Reference Design data plane functionality is included in the Mesh Switch IP, shown in Figure 4.
All documentation and design files for the Full Mesh Fabric Reference Design are included with the purchase of a Design Kit.
Figure 3: IBM PowerPC Control Plane Logic
MultiBERT Test Environment:
Included with the design kit is a complete test environment, called MultiBERT, that is used to exercise the design with a comprehensive suite of test features. MultiBERT runs on a host computer (not included) and uses the example design native on the ATCA board. MultiBERT is the primary 'bring up' environment to get your development started and to validate your design. The following is a list of some of the key MultiBERT features:
-
Up to 120 simultaneous full duplex serial connections, in a
16-slot full mesh chassis
-
Automatic slot identification and backplane modeling, with
provision for user-defined backplane models
-
Control of the following settings through the MultiBERT GUI,
running on Windows:
-
Eight different serial test data patterns
-
Two different settings of low speed clock reference
-
Use of Multi-Gigabit Transceiver serial and parallel loopback
-
Multi-Gigabit Transceiver transmit polarity
-
Control of the following settings through FPGA compile-
time configuration:
-
Multi-Gigabit Transceiver Transmit Pre-Emphasis
-
Multi-Gigabit Transceiver Transmit Differential Voltage
-
Multi-Gigabit Transceiver Reference Clock Source
-
Reporting of the following statistics through the MultiBERT GUI:
Figure 4: Mesh Fabric Design Block Diagram
Feature List:
Included with the Design Kit:
Optional elements:
-
Power supply
-
Card cage
-
Board level and FPGA design services
-
Supporting Intellectual Property cores
-
Xilinx development software tools
-
Training on Virtex-II Pro and designing with Multi-Gigabit Transceivers
Other related products and information:
Intel ATCA Boards and Chassis
Intel has a set of complimentary products that can be used to augment your Avnet/Xilinx ATCA board. These include a single board computer a 14U Chassis and a Chassis Management Module. Included with these boards are BIOS and Firmware to help speed your development cycle. For current information on Intel boards and chassis you can order from Avnet visit this url. http://www.intel.com/design/network/products/cbp/atca/index.htm
Xilinx Intellectual Property Cores
Xilinx has a variety of Intellectual Property (IP) Cores that are compatible with the Avnet/Xilinx ATCA Development Platform. Current IP Cores include support for: 1G & 10G Ethernet, Aurora, PCI Express, XAUI, RapidIO & Serial Rapid IO, Advanced Switching, SPI-4.2, Fibre Channel, SONET/SDH, CSIX, XGMII, HyperTransport, and PCI/PCI-X. Visit this url and search for the IP Cores you need in your system and then order them from Avnet.
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Intellectual+Property
Xilinx ATCA Web Portal
Xilinx has a comprehensive ATCA site that is a good starting point for learning all things ATCA. Visit this url to get started.
http://www.xilinx.com/esp/wired/optical/xlnx_net/atca_dev.htm
Avnet Authored ATCA Article in Xilinx Xcell Journal
Visit this web page to read over the Xcell Journal article on the Avnet/Xilinx ATCA Development Platform.
http://www.xilinx.com/publications/xcellonline/xcell_49/xc_pdf/xc_avnet49.pdf | 
